1. Field of the Invention
The present invention relates to semiconductor manufacturing process. More particularly, the present invention relates to a method for manufacturing an anti-punch through semiconductor device.
2. Description of Related Art
As the demand for higher integration of circuits increases, the design of a circuit device mandates a diminishment of the device dimension. When the dimension of a semiconductor device gradually reduces to a certain degree, the distance between devices correspondingly reduces. Hence, the various problems generated from fabricating a highly integrated device will become apparent. Accordingly, the industry is focused on developing a compact and a highly integrated semiconductor device with desirable qualities.
FIG. 1 is a cross-sectional diagram of a conventional semiconductor device. The semiconductor device includes a substrate 100, a dielectric layer 102, a trench device 104 and a doped region 106. The dielectric layer 102 is disposed above the substrate, while the trench device 104 is disposed in parts of the substrate 100 and the dielectric layer 102. The doped region 106 is configured in the substrate 100 under the trench device 104.
As the integration of a semiconductor device gradually increases, the conventional fabrication method of the semiconductor device confronts with many challenges. For example, as the integration of the semiconductor device increases, the distance between neighboring trench devices 104 correspondingly reduces. Therefore, a punch through (as depicted by arrow 108 in FIG. 1) between two neighboring doped regions easily occurs. Consequently, an abnormal electrical conduction between the neighboring trench devices 104 is developed, leading to poor operating speed and efficiency of the device. Further, a short or an open of the device is resulted, wherein the reliability and the yield of the entire process may be affected.